The term “receiver” is used herein in a broad sense to denote any device capable of receiving and decoding data that has been transmitted over a serial link or other link (and optionally also performing additional functions, which can include decrypting the received data and other operations related to decoding, reception, or decryption of the received data). For example, the term receiver can denote a transceiver that performs the functions of a transmitter as well as the functions of a receiver.
The term “CDR” is used herein to denote a clock and data recovery device. Typically, a receiver includes a CDR. Throughout the disclosure, CDRs are described as devices that receive “data” and generate at least one sequence of samples of the data. It should be understood that the “data” can be a signal indicative of a clock, or a signal indicative of an arbitrary sequence of binary bits of data. Some CDRs include circuitry for recovering both a clock and data from one or more received signals. A “CDR,” as the term is used herein (including in the claims) need not include circuitry for recovering both a clock and data from one or more received signals.
The expression “phase detector” is used herein to denote a circuit that determines the phase error (φΔ) present between a sampling clock and data (being sampled by the clock). A phase detector (“PD”) is thus useful with a data sampling circuit including a feedback loop for controlling the phase of a sampling clock.
It should be understood that when phase error (φΔ), between a sampling clock and a data signal being sampled using the clock, is expressed herein in degrees, the quantity “360 degrees” corresponds to one bit time of the data signal (with “bit time” being synonymous with “bit period” and denoting the inverse of the bit rate) and typically does not correspond to one period of the sampling clock. Typically, a sampling clock employed in accordance with the invention (e.g., data sampling clock “dCLK” or edge sampling clock “xCLK” discussed below) has frequency equal to f/N, where “f” is the bit rate of the data signal being sampled and N is an integer greater than one (for example, N=4 or N is another small integer). It should also be understood that when a clock is referred to herein as being “X” degrees out of phase with respect to another clock having the same frequency (e.g., when a raw edge sampling clock is said to be 180 degrees out of phase with a raw data sampling clock), the quantity “360 degrees” corresponds to one bit time of a data signal being sampled using the clocks, and typically does not correspond to one period of either one of the clocks. For example, in the below-described preferred implementation of the FIG. 3(a) system, raw data sampling clock “idCLK[0]” and raw edge sampling clock “ixCLK[0]” are referred to as being 180 degrees out of phase with respect to each other because clock “ixCLK[0]” lags clock “idCLK[0]” by one half of a bit time, and “ixCLK[0]” and raw edge sampling clock “idCLK[1]” are 180 degrees out of phase with respect to each other because clock “idCLK[1]” lags clock “ixCLK[0]” by one half of a bit time.
The expression “binary phase detector” is used herein to denote a circuit that determines whether the phase error (φΔ) present between a sampling clock and data (being sampled by the clock) is positive or negative, without determining the magnitude of the phase error.
A binary phase detector (binary PD) based on a 2× oversampling technique has been widely used in transceivers (for receiving data transmitted over high speed serial links) due to its simple structure. A transceiver including such a PD is described in the paper by A. Fiedler, et al., entitled “A 1.0625 Gbps Transceiver with 2×-Oversampling and Transmit Signal Pre-Emphasis,” ISSCC Digest of Technical Papers, pp. 238-239, February 1997. However, the loop characteristics of a CDR using such a binary PD are dependent on the jitter amplitude of the input data stream and the CDR might not be robust over a wide range of jitter amplitude. An example of this uncertainty is illustrated in FIG. 1(a), which includes data eye diagrams, 2× based sampling clocks, edge distribution diagrams, and Ia−φΔ curves for large and small amounts of jitter (where Iavg denotes average pumping current), assuming that some phase error (φΔ) is present between the sampling clocks and data. Typically, a CDR including a binary PD asserts a positive charge pump current (IP) to cause advancement of the sampling clock phase when the sampling clock lags the data, and a negative charge pump current (−IP) to cause retardation of the sampling clock phase when the sampling clock leads the data. Ideally (i.e., in the absence of jitter), the average pumping current (Iavg) is equal to the charge pump current (IP) when the sampling clock lags the data and the average pumping current (Iavg) is equal to the negative charge pump current (−IP) when the sampling clock leads the data. However, in a real world application in which there is high frequency jitter, the absolute value of the average pumping current (Iavg) is less than the absolute value of the charge pump current (when the sampling clock leads or lags the data) since the binary PD makes an up/down decision (a decision as to whether to increase or decrease the sampling clock phase) per each data transition and Iavg is proportional to an average difference of the up/down decisions (represented by the shaded area in FIG. 1(a)). Therefore, for the same charge pump current, larger jitter reduces the absolute magnitude of the average pumping current and reduces the gain KPD (the slope of the Iavg versusφΔ curve). So, the gain KPD and the absolute magnitude of Iavg are inversely proportional to the amount of jitter, as indicated by the bottom graph in FIG. 1(a).
It should be understood that the expression “average” pumping current (Iavg) herein denotes an average of instantaneous values of the charge pump current over a time interval in which averaged phase error (averaged φΔ) is positive or negative; not a time interval over which averaged phase error (averaged φΔ) is zero. An average of instantaneous values of charge pump current, over a time interval in which averaged phase error (averaged φΔ) is zero, would be zero (or nearly zero) and would typically be neither proportional nor inversely proportional to the amount of jitter.
The unstable gain (KPD) due to jitter variation, of a conventional CDR that includes a binary PD based on a 2× oversampling technique as described with reference to FIG. 1(a), results in unreliable CDR loop characteristics.
Conventional CDRs that include 2× oversampling PDs do not support any method to measure jitter. Estimation of jitter can be accomplished in accordance with the invention using a modified version of the “dead zone” PD described in Y. Moon, et al., “A 0.6-2.5 Gbaud CMOS Tracked 3× Oversampling Transceiver with Dead Zone Phase Detection for Robust Clock/Data Recovery,” ISSCC Digest of Technical Papers, pp. 212-213, February 2001, and in S. Lee, et al., “A 5 Gb/s 0.25 μm CMOS Jitter-Tolerant Variable-Interval Oversampling Clock/Data Recovery Circuit,” ISSCC Digest of Technical Papers, pp. 256-257, February 2002. Because the dead zone PD described in the cited papers by Moon, et al. and Lee, et al. is based on 3× oversampling, a CDR including the dead zone PD must employ 3× oversampling and thus requires more hardware to implement and consumes more power than does a CDR that employs 2× oversampling. The noted problems of the prior art can be overcome in accordance with the invention by using a CDR that employs 2× oversampling, has reliable CDR loop characteristics, and includes an embodiment of the inventive alternating edge sampling phase detector (“AES PD”) which establishes a dead zone.